計算機體系結(jié)構(gòu)：量化研究方法（英文版·第5版）簡介，目錄書摘
2020-01-13 15:11
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計算機體系結(jié)構(gòu)：量化研究方法（英文版·第5版）
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《計算機體系結(jié)構(gòu)：量化研究方法（英文版·第5版）》特點：
更新相關(guān)內(nèi)容以覆蓋移動計算變革，并強調(diào)當今體系結(jié)構(gòu)重要的兩個主題：存儲器層次結(jié)構(gòu)和各種并行技術(shù)。
每章中的"Putting It All Together"小節(jié)關(guān)注了業(yè)界的各種技術(shù)，包括ARM Cortex-A8、Intel Core i7、NVIDIAGTX-280和GTX-480 GPU，以及一種Google倉庫級計算機。
每章都設計了常規(guī)主題：能力、性能、成本、可依賴性、保護、編程模型和新趨勢。
書中包括3個附錄，另外8個附錄可以在原出版社網(wǎng)站在線得到。
每章后都設置了由工業(yè)界和學術(shù)界專家提供的經(jīng)過更新的案例研究，以及與之配套的全新練習題。
內(nèi)容簡介: 《計算機體系結(jié)構(gòu)：量化研究方法（英文版·第5版）》堪稱計算機系統(tǒng)結(jié)構(gòu)學科的“圣經(jīng)”，是計算機設計領(lǐng)域?qū)W生和實踐者的必讀經(jīng)典。本書系統(tǒng)地介紹了計算機系統(tǒng)的設計基礎、存儲器層次結(jié)構(gòu)設計、指令級并行及其開發(fā)、數(shù)據(jù)級并行、GPU體系結(jié)構(gòu)、線程級并行和倉庫級計算機等。
現(xiàn)今計算機界處于變革之中：移動客戶端和云計算正在成為驅(qū)動程序設計和硬件創(chuàng)新的主流范型。因此在這個版中，作者考慮到這個巨大的變化，重點關(guān)注了新的平臺（個人移動設備和倉庫級計算機）和新的體系結(jié)構(gòu)（多核和GPU），不僅介紹了移動計算和云計算等新內(nèi)容，還討論了成本、性能、功耗、可靠性等設計要素。每章都有兩個真實例子，一個來源于手機，另一個來源于數(shù)據(jù)中心，以反映計算機界正在發(fā)生的革命性變革。
本書內(nèi)容豐富，既介紹了當今計算機體系結(jié)構(gòu)的研究成果，也引述了許多計算機系統(tǒng)設計開發(fā)方面的實踐經(jīng)驗。另外，各章結(jié)尾還附有大量的習題和參考文獻。本書既可以作為高等院校計算機專業(yè)高年級本科生和研究生學習“計算機體系結(jié)構(gòu)”課程的教材或參考書，也可供與計算機相關(guān)的專業(yè)人士學習參考。
現(xiàn)今計算機界處于變革之中：移動客戶端和云計算正在成為驅(qū)動程序設計和硬件創(chuàng)新的主流范型。因此在這個版中，作者考慮到這個巨大的變化，重點關(guān)注了新的平臺（個人移動設備和倉庫級計算機）和新的體系結(jié)構(gòu)（多核和GPU），不僅介紹了移動計算和云計算等新內(nèi)容，還討論了成本、性能、功耗、可靠性等設計要素。每章都有兩個真實例子，一個來源于手機，另一個來源于數(shù)據(jù)中心，以反映計算機界正在發(fā)生的革命性變革。
本書內(nèi)容豐富，既介紹了當今計算機體系結(jié)構(gòu)的研究成果，也引述了許多計算機系統(tǒng)設計開發(fā)方面的實踐經(jīng)驗。另外，各章結(jié)尾還附有大量的習題和參考文獻。本書既可以作為高等院校計算機專業(yè)高年級本科生和研究生學習“計算機體系結(jié)構(gòu)”課程的教材或參考書，也可供與計算機相關(guān)的專業(yè)人士學習參考。
作者簡介: John L.Hennessy，斯坦福大學校長，IEEE和ACM會士，美國國家工程研究院院士及美國科學藝術(shù)研究院院士。Hennessy教授因為在RISC技術(shù)方面做出了突出貢獻而榮獲2001年的Eckert-Mauchly獎章，他也是2001年Seymour Cray計算機工程獎得主，并且和本書另外一位作者David A. Patterson分享了2000年John von Neumann獎。
David A. Patterson 加州大學伯克利分校計算機科學系主任、教授，美國國家工程研究院院士，IEEE和ACM會士，曾因成功的啟發(fā)式教育方法被IEEE授予James H. Mulligan，Jr.教育獎章。他因為對RISC技術(shù)的貢獻而榮獲1995年IEEE技術(shù)成就獎，而在RAID技術(shù)方面的成就為他贏得了1999年IEEE Reynold Johnson4R息存儲獎。2000年他John L. Hennessy分享了John yon Neumann獎。
David A. Patterson 加州大學伯克利分校計算機科學系主任、教授，美國國家工程研究院院士，IEEE和ACM會士，曾因成功的啟發(fā)式教育方法被IEEE授予James H. Mulligan，Jr.教育獎章。他因為對RISC技術(shù)的貢獻而榮獲1995年IEEE技術(shù)成就獎，而在RAID技術(shù)方面的成就為他贏得了1999年IEEE Reynold Johnson4R息存儲獎。2000年他John L. Hennessy分享了John yon Neumann獎。
目錄:Foreword
Preface
Acknowledgments
Chapter 1 Fundamentals of Quantitative Design and Analysis
1.1 Introduction
1.2 Classes of Computers
1.3 Defining Computer Architecture
1.4 Trends in Technology
1.5 Trends in Power and Energy in Integrated Circuits
1.6 Trends in Cost
1.7 Dependability
1.8 Measuring, Reporting, and Summarizing Performance
1.9 Quantitative Principles of Computer Design
1.10 Putting It All Together: Performance, Price, and Power
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspectives and References Case Studies and Exercises by Diana Franklin
Chapter 2 Memory Hierarchy Design
2.1 Introduction
2.2 Ten Advanced Optimizations of Cache Performance
2.3 Memory Technology and Optimizations
2.4 Protection: Virtual Memory and Virtual Machines
2.5 Crosscutting Issues: The Design of Memory Hierarchies
2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-AS and Intel Core i7
2.7 Fallacies and Pitfalls
2.8 Concluding Remarks: Looking Ahead
2.9 Historical Perspective and References Case Studies and Exercises by Norman P. Jouppi, Naveen Muralimanohar, and Sheng Li
Chapter 3 nstruction-Level Parallelism and Its Exploitation
3.1 Instruction-Level Parallelism: Concepts and Challenges
3.2 Basic Compiler Techniques for Exposing ILP
3.3 Reducing Branch Costs with Advanced Branch Prediction
3.4 Overcoming Data Hazards with Dynamic Scheduling
3.5 Dynamic Scheduling: Examples and the Algorithm
3.6 Hardware-Based Speculation
3.7 Exploiting ILP Using Multiple Issue and Static Scheduling
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
3.9 Advanced Techniques for Instruction Delivery and Speculation
3.10 Studies of the Limitations oflLP
3.11 Cross-Cutting Issues: ILP Approaches and the Memory System
3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput
3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-AS
3.14 Fallacies and Pitfalls
3.15 Concluding Remarks: What's Ahead?
3.16 Historical Perspective and References Case Studies and Exercises by Jason D. Bakos and Robert R Colwell
Chapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures
4.1 Introduction
4.2 Vector Architecture
4.3 SIMD Instruction Set Extensions for Multimedia
4.4 Graphics Processing Units
4.5 Detecting and Enhancing Loop-Level Parallelism
4.6 Crosscutting Issues
4.7 Putting It All Together: Mobile versus Server GPUS and Tesla versus Core i7
4.8 Fallacies and Pitfalls
4.9 Concluding Remarks
4.10 Historical Perspective and References Case Study and Exercises by Jason D. Bakos
Chapter 5 Thread-Level Parallelism
5.1 Introduction
5.2 Centralized Shared-Memory Architectures
5.3 Performance of Symmetric Shared-Memory Multiprocessors
……
Chapter6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism
Appendix A Instruction Set Principles
Appendix B Review of Memory Hierarchy
Appendix C Pipelining: Basic and Intermediate Concepts
Preface
Acknowledgments
Chapter 1 Fundamentals of Quantitative Design and Analysis
1.1 Introduction
1.2 Classes of Computers
1.3 Defining Computer Architecture
1.4 Trends in Technology
1.5 Trends in Power and Energy in Integrated Circuits
1.6 Trends in Cost
1.7 Dependability
1.8 Measuring, Reporting, and Summarizing Performance
1.9 Quantitative Principles of Computer Design
1.10 Putting It All Together: Performance, Price, and Power
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspectives and References Case Studies and Exercises by Diana Franklin
Chapter 2 Memory Hierarchy Design
2.1 Introduction
2.2 Ten Advanced Optimizations of Cache Performance
2.3 Memory Technology and Optimizations
2.4 Protection: Virtual Memory and Virtual Machines
2.5 Crosscutting Issues: The Design of Memory Hierarchies
2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-AS and Intel Core i7
2.7 Fallacies and Pitfalls
2.8 Concluding Remarks: Looking Ahead
2.9 Historical Perspective and References Case Studies and Exercises by Norman P. Jouppi, Naveen Muralimanohar, and Sheng Li
Chapter 3 nstruction-Level Parallelism and Its Exploitation
3.1 Instruction-Level Parallelism: Concepts and Challenges
3.2 Basic Compiler Techniques for Exposing ILP
3.3 Reducing Branch Costs with Advanced Branch Prediction
3.4 Overcoming Data Hazards with Dynamic Scheduling
3.5 Dynamic Scheduling: Examples and the Algorithm
3.6 Hardware-Based Speculation
3.7 Exploiting ILP Using Multiple Issue and Static Scheduling
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
3.9 Advanced Techniques for Instruction Delivery and Speculation
3.10 Studies of the Limitations oflLP
3.11 Cross-Cutting Issues: ILP Approaches and the Memory System
3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput
3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-AS
3.14 Fallacies and Pitfalls
3.15 Concluding Remarks: What's Ahead?
3.16 Historical Perspective and References Case Studies and Exercises by Jason D. Bakos and Robert R Colwell
Chapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures
4.1 Introduction
4.2 Vector Architecture
4.3 SIMD Instruction Set Extensions for Multimedia
4.4 Graphics Processing Units
4.5 Detecting and Enhancing Loop-Level Parallelism
4.6 Crosscutting Issues
4.7 Putting It All Together: Mobile versus Server GPUS and Tesla versus Core i7
4.8 Fallacies and Pitfalls
4.9 Concluding Remarks
4.10 Historical Perspective and References Case Study and Exercises by Jason D. Bakos
Chapter 5 Thread-Level Parallelism
5.1 Introduction
5.2 Centralized Shared-Memory Architectures
5.3 Performance of Symmetric Shared-Memory Multiprocessors
……
Chapter6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism
Appendix A Instruction Set Principles
Appendix B Review of Memory Hierarchy
Appendix C Pipelining: Basic and Intermediate Concepts
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